| Titre : |
Closing the Gap Between ASIC & Custom : tools and techniques for high-performance ASIC design |
| Type de document : |
texte imprimé |
| Auteurs : |
David Chinnery, Auteur ; Kurt Keutzer, Auteur |
| Editeur : |
Boston, Dordrecht, London : Kluwer Academic Publishers |
| Année de publication : |
2002 |
| Importance : |
414 p. |
| Présentation : |
couv. ill. en coul., ill. |
| Format : |
24 cm. |
| ISBN/ISSN/EAN : |
978-1-4020-7113-3 |
| Langues : |
Anglais (eng) |
| Catégories : |
SEMI CONDUCTEURS
|
| Mots-clés : |
ASIC Flip-Flop Standard architecture integrated circuit layout logic microprocessor optimization transistor |
| Index. décimale : |
27-05 Microélectronique |
| Résumé : |
This book carefully details design tools and techniques for high-performance ASIC design. Using these techniques, the performance of ASIC designs can be improved by two to three times.
Important topics include:
-Improving performance through microarchitecture;
-Timing-driven floorplanning;
-Controlling and exploiting clock skew;
-High performance latch-based design in an ASIC methodology;
-Automatically identifying and synthesizing complex logic gates;
-Automated cell sizing to increase performance and reduce power;
-Controlling process variation.
These techniques are illustrated by designs running two to three times the speed of typical ASICs in the same process generation. |
| Note de contenu : |
Table of Contents
1. Introduction and Overview of the Book
Contributing Factors.
2. Improving Performance through Microarchitecture
3. Reducing the Timing Overhead
4. High-Speed Logic, Circuits, Libraries and Layout
5. Finding Peak Performance in a Process
Design Techniques.
6. Physical Prototyping Plans for High Performance
7. Automatic Replacement of Flip-Flops by Latches in ASIC's
8. Useful-Skew Clock Synthesis Boosts ASIC Performance
9. Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing
10. Design Optimization with Automated Flex-Cell Creation
11. Exploiting Structure and Managing Wires to Increase Density and Performance
12. Semi-Custom Methods in a High-Performance Microprocessor Design
13. Controlling Uncertainty in High Frequency Designs
14. Increasing Circuit Performance through Statistical Design Techniques
Design Examples.
15. Achieving 550MHz in a Standard Cell ASIC Methodology
16. The iCORE® 520MHz Synthesizable CPU Core
17. Creating Synthesizable ARM Processors with Near Custom Performance |
Closing the Gap Between ASIC & Custom : tools and techniques for high-performance ASIC design [texte imprimé] / David Chinnery, Auteur ; Kurt Keutzer, Auteur . - Boston, Dordrecht, London : Kluwer Academic Publishers, 2002 . - 414 p. : couv. ill. en coul., ill. ; 24 cm. ISBN : 978-1-4020-7113-3 Langues : Anglais ( eng)
| Catégories : |
SEMI CONDUCTEURS
|
| Mots-clés : |
ASIC Flip-Flop Standard architecture integrated circuit layout logic microprocessor optimization transistor |
| Index. décimale : |
27-05 Microélectronique |
| Résumé : |
This book carefully details design tools and techniques for high-performance ASIC design. Using these techniques, the performance of ASIC designs can be improved by two to three times.
Important topics include:
-Improving performance through microarchitecture;
-Timing-driven floorplanning;
-Controlling and exploiting clock skew;
-High performance latch-based design in an ASIC methodology;
-Automatically identifying and synthesizing complex logic gates;
-Automated cell sizing to increase performance and reduce power;
-Controlling process variation.
These techniques are illustrated by designs running two to three times the speed of typical ASICs in the same process generation. |
| Note de contenu : |
Table of Contents
1. Introduction and Overview of the Book
Contributing Factors.
2. Improving Performance through Microarchitecture
3. Reducing the Timing Overhead
4. High-Speed Logic, Circuits, Libraries and Layout
5. Finding Peak Performance in a Process
Design Techniques.
6. Physical Prototyping Plans for High Performance
7. Automatic Replacement of Flip-Flops by Latches in ASIC's
8. Useful-Skew Clock Synthesis Boosts ASIC Performance
9. Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing
10. Design Optimization with Automated Flex-Cell Creation
11. Exploiting Structure and Managing Wires to Increase Density and Performance
12. Semi-Custom Methods in a High-Performance Microprocessor Design
13. Controlling Uncertainty in High Frequency Designs
14. Increasing Circuit Performance through Statistical Design Techniques
Design Examples.
15. Achieving 550MHz in a Standard Cell ASIC Methodology
16. The iCORE® 520MHz Synthesizable CPU Core
17. Creating Synthesizable ARM Processors with Near Custom Performance |
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