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Affiner la recherche Interroger des sources externesAdvanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® / Himanshu Bhatnagar
Titre : Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® Type de document : texte imprimé Auteurs : Himanshu Bhatnagar, Auteur Mention d'édition : 2nd. ed. Editeur : Boston, Dordrecht, London : Kluwer Academic Publishers Année de publication : 2002 Importance : 328 p. Présentation : couv. ill. en coul., ill. Format : 24,1 cm. ISBN/ISSN/EAN : 978-0-7923-7644-6 Langues : Anglais (eng) Catégories : SEMI CONDUCTEURS Index. décimale : 27-05 Microélectronique Résumé : Advanced ASIC Chip Synthesis: Using Synopsys® DesignCompiler® Physical Compiler® and PrimeTime®, SecondEdition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail.
The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.
Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.Note de contenu : Sommaire
Chapter 1. ASIC Design Methodology.
2. Tutorial.
3. Basic Concepts.
4. Synopsis Technology Library.
5. Partitioning and Coding Styles.
6. Constraining Designs.
7. Optimizing Designs.
8. Design for Test.
9. Links to Layout & Post Layout OPT.
10. Physical Synthesis.
11. SDF Generation.
12. Primetime Basics.
13. Static Timing Analysis.
Appendix A.
Appendix B.
Index.Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® [texte imprimé] / Himanshu Bhatnagar, Auteur . - 2nd. ed. . - Boston, Dordrecht, London : Kluwer Academic Publishers, 2002 . - 328 p. : couv. ill. en coul., ill. ; 24,1 cm.
ISBN : 978-0-7923-7644-6
Langues : Anglais (eng)
Catégories : SEMI CONDUCTEURS Index. décimale : 27-05 Microélectronique Résumé : Advanced ASIC Chip Synthesis: Using Synopsys® DesignCompiler® Physical Compiler® and PrimeTime®, SecondEdition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail.
The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.
Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.Note de contenu : Sommaire
Chapter 1. ASIC Design Methodology.
2. Tutorial.
3. Basic Concepts.
4. Synopsis Technology Library.
5. Partitioning and Coding Styles.
6. Constraining Designs.
7. Optimizing Designs.
8. Design for Test.
9. Links to Layout & Post Layout OPT.
10. Physical Synthesis.
11. SDF Generation.
12. Primetime Basics.
13. Static Timing Analysis.
Appendix A.
Appendix B.
Index.Exemplaires(1)
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Titre : Battery Management Systems: Design by Modelling Type de document : texte imprimé Auteurs : Henk Jan Bergveld, Auteur ; Wanda S. Kruijt, Auteur ; Peter H.L. Notten, Auteur Editeur : Boston, Dordrecht, London : Kluwer Academic Publishers Année de publication : 2002 Collection : Philips Research Book Series ISBN/ISSN/EAN : 978-1-4020-0832-0 Langues : Français (fre) Catégories : LES ÉNERGIES Index. décimale : 21-01 L'énergie nucléaire Résumé : Battery Management Systems - Design by Modelling describes the design of Battery Management Systems (BMS) with the aid of simulation methods. The basic tasks of BMS are to ensure optimum use of the energy stored in the battery (pack) that powers a portable device and to prevent damage inflicted on the battery (pack). This becomes increasingly important due to the larger power consumption associated with added features to portable devices on the one hand and the demand for longer run times on the other hand. In addition to explaining the general principles of BMS tasks such as charging algorithms and State-of-Charge (SoC) indication methods, the book also covers real-life examples of BMS functionality of practical portable devices such as shavers and cellular phones.
Simulations offer the advantage over measurements that less time is needed to gain knowledge of a battery's behaviour in interaction with other parts in a portable device under a wide variety of conditions. This knowledge can be used to improve the design of a BMS, even before a prototype of the portable device has been built. The battery is the central part of a BMS and good simulation models that can be used to improve the BMS design were previously unavailable. Therefore, a large part of the book is devoted to the construction of simulation models for rechargeable batteries. With the aid of several illustrations it is shown that design improvements can indeed be realized with the presented battery models. Examples include an improved charging algorithm that was elaborated in simulations and verified in practice and a new SoC indication system that was developed showing promising results.
The contents of Battery Management Systems - Design by Modelling is based on years of research performed at the Philips Research Laboratories. The combination of basic and detailed descriptions of battery behaviour both in chemical and electrical terms makes this book truly multidisciplinary. It can therefore be read both by people with an (electro)chemical and an electrical engineering background.Note de contenu : Table of contents
List of abbreviations.
List of symbols.
Series preface.
Preface.
1. Introduction.
2. Battery Management Systems.
3. Basic information on batteries.
4. Battery modelling.
5. Battery charging algorithms.
6. Battery State-of-Charge indication.
7. Optimum supply strategies for Power Amplifiers in cellular phones.
8. General conclusions.
About the authors.
Index.Battery Management Systems: Design by Modelling [texte imprimé] / Henk Jan Bergveld, Auteur ; Wanda S. Kruijt, Auteur ; Peter H.L. Notten, Auteur . - Boston, Dordrecht, London : Kluwer Academic Publishers, 2002. - (Philips Research Book Series) .
ISBN : 978-1-4020-0832-0
Langues : Français (fre)
Catégories : LES ÉNERGIES Index. décimale : 21-01 L'énergie nucléaire Résumé : Battery Management Systems - Design by Modelling describes the design of Battery Management Systems (BMS) with the aid of simulation methods. The basic tasks of BMS are to ensure optimum use of the energy stored in the battery (pack) that powers a portable device and to prevent damage inflicted on the battery (pack). This becomes increasingly important due to the larger power consumption associated with added features to portable devices on the one hand and the demand for longer run times on the other hand. In addition to explaining the general principles of BMS tasks such as charging algorithms and State-of-Charge (SoC) indication methods, the book also covers real-life examples of BMS functionality of practical portable devices such as shavers and cellular phones.
Simulations offer the advantage over measurements that less time is needed to gain knowledge of a battery's behaviour in interaction with other parts in a portable device under a wide variety of conditions. This knowledge can be used to improve the design of a BMS, even before a prototype of the portable device has been built. The battery is the central part of a BMS and good simulation models that can be used to improve the BMS design were previously unavailable. Therefore, a large part of the book is devoted to the construction of simulation models for rechargeable batteries. With the aid of several illustrations it is shown that design improvements can indeed be realized with the presented battery models. Examples include an improved charging algorithm that was elaborated in simulations and verified in practice and a new SoC indication system that was developed showing promising results.
The contents of Battery Management Systems - Design by Modelling is based on years of research performed at the Philips Research Laboratories. The combination of basic and detailed descriptions of battery behaviour both in chemical and electrical terms makes this book truly multidisciplinary. It can therefore be read both by people with an (electro)chemical and an electrical engineering background.Note de contenu : Table of contents
List of abbreviations.
List of symbols.
Series preface.
Preface.
1. Introduction.
2. Battery Management Systems.
3. Basic information on batteries.
4. Battery modelling.
5. Battery charging algorithms.
6. Battery State-of-Charge indication.
7. Optimum supply strategies for Power Amplifiers in cellular phones.
8. General conclusions.
About the authors.
Index.Exemplaires(1)
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Titre : Closing the Gap Between ASIC & Custom : tools and techniques for high-performance ASIC design Type de document : texte imprimé Auteurs : David Chinnery, Auteur ; Kurt Keutzer, Auteur Editeur : Boston, Dordrecht, London : Kluwer Academic Publishers Année de publication : 2002 Importance : 414 p. Présentation : couv. ill. en coul., ill. Format : 24 cm. ISBN/ISSN/EAN : 978-1-4020-7113-3 Langues : Anglais (eng) Catégories : SEMI CONDUCTEURS Mots-clés : ASIC Flip-Flop Standard architecture integrated circuit layout logic microprocessor optimization transistor Index. décimale : 27-05 Microélectronique Résumé : This book carefully details design tools and techniques for high-performance ASIC design. Using these techniques, the performance of ASIC designs can be improved by two to three times.
Important topics include:
-Improving performance through microarchitecture;
-Timing-driven floorplanning;
-Controlling and exploiting clock skew;
-High performance latch-based design in an ASIC methodology;
-Automatically identifying and synthesizing complex logic gates;
-Automated cell sizing to increase performance and reduce power;
-Controlling process variation.
These techniques are illustrated by designs running two to three times the speed of typical ASICs in the same process generation.Note de contenu : Table of Contents
1. Introduction and Overview of the Book
Contributing Factors.
2. Improving Performance through Microarchitecture
3. Reducing the Timing Overhead
4. High-Speed Logic, Circuits, Libraries and Layout
5. Finding Peak Performance in a Process
Design Techniques.
6. Physical Prototyping Plans for High Performance
7. Automatic Replacement of Flip-Flops by Latches in ASIC's
8. Useful-Skew Clock Synthesis Boosts ASIC Performance
9. Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing
10. Design Optimization with Automated Flex-Cell Creation
11. Exploiting Structure and Managing Wires to Increase Density and Performance
12. Semi-Custom Methods in a High-Performance Microprocessor Design
13. Controlling Uncertainty in High Frequency Designs
14. Increasing Circuit Performance through Statistical Design Techniques
Design Examples.
15. Achieving 550MHz in a Standard Cell ASIC Methodology
16. The iCORE® 520MHz Synthesizable CPU Core
17. Creating Synthesizable ARM Processors with Near Custom PerformanceClosing the Gap Between ASIC & Custom : tools and techniques for high-performance ASIC design [texte imprimé] / David Chinnery, Auteur ; Kurt Keutzer, Auteur . - Boston, Dordrecht, London : Kluwer Academic Publishers, 2002 . - 414 p. : couv. ill. en coul., ill. ; 24 cm.
ISBN : 978-1-4020-7113-3
Langues : Anglais (eng)
Catégories : SEMI CONDUCTEURS Mots-clés : ASIC Flip-Flop Standard architecture integrated circuit layout logic microprocessor optimization transistor Index. décimale : 27-05 Microélectronique Résumé : This book carefully details design tools and techniques for high-performance ASIC design. Using these techniques, the performance of ASIC designs can be improved by two to three times.
Important topics include:
-Improving performance through microarchitecture;
-Timing-driven floorplanning;
-Controlling and exploiting clock skew;
-High performance latch-based design in an ASIC methodology;
-Automatically identifying and synthesizing complex logic gates;
-Automated cell sizing to increase performance and reduce power;
-Controlling process variation.
These techniques are illustrated by designs running two to three times the speed of typical ASICs in the same process generation.Note de contenu : Table of Contents
1. Introduction and Overview of the Book
Contributing Factors.
2. Improving Performance through Microarchitecture
3. Reducing the Timing Overhead
4. High-Speed Logic, Circuits, Libraries and Layout
5. Finding Peak Performance in a Process
Design Techniques.
6. Physical Prototyping Plans for High Performance
7. Automatic Replacement of Flip-Flops by Latches in ASIC's
8. Useful-Skew Clock Synthesis Boosts ASIC Performance
9. Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing
10. Design Optimization with Automated Flex-Cell Creation
11. Exploiting Structure and Managing Wires to Increase Density and Performance
12. Semi-Custom Methods in a High-Performance Microprocessor Design
13. Controlling Uncertainty in High Frequency Designs
14. Increasing Circuit Performance through Statistical Design Techniques
Design Examples.
15. Achieving 550MHz in a Standard Cell ASIC Methodology
16. The iCORE® 520MHz Synthesizable CPU Core
17. Creating Synthesizable ARM Processors with Near Custom PerformanceExemplaires(2)
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Titre : A designer's guide to vhdl synthesis Type de document : texte imprimé Auteurs : Douglas E. Ott, Auteur ; Thomas J. Wilderotter, Auteur Editeur : Boston, Dordrecht, London : Kluwer Academic Publishers Année de publication : 1994 Importance : 306 p. Présentation : couv. ill.,ill. Format : 24 cm. ISBN/ISSN/EAN : 978-0-7923-9472-3 Langues : Anglais (eng) Catégories : MICRO INFORMATIQUE Index. décimale : 24-03 Programmation des microsystèmes et microprocesseurs Résumé : A Designer's Guide to VHDL Synthesis is intended for both design engineers who want to use VHDL-based logic synthesis ASICs and for managers who need to gain a practical understanding of the issues involved in using this technology. The emphasis is placed more on practical applications of VHDL and synthesis based on actual experiences, rather than on a more theoretical approach to the language.
VHDL and logic synthesis tools provide very powerful capabilities for ASIC design, but are also very complex and represent a radical departure from traditional design methods. This situation has made it difficult to get started in using this technology for both designers and management, since a major learning effort and `culture' change is required. A Designer's Guide to VHDL Synthesis has been written to help design engineers and other professionals successfully make the transition to a design methodology based on VHDL and log synthesis instead of the more traditional schematic based approach. While there are a number of texts on the VHDL language and its use in simulation, little has been written from a designer's viewpoint on how to use VHDL and logic synthesis to design real ASIC systems. The material in this book is based on experience gained in successfully using these techniques for ASIC design and relies heavily on realistic examples to demonstrate the principles involved.Note de contenu : Contents
Chapter 1 Introduction
Chapter 2 Making the Transition to VHDL Synthesis
Chapter 3 VHDL Background for Synthesis
Chapter 4 Synthesis of Sequential Circuits
Chapter 5 Sequential Counter Applications
Chapter 6 Control Logic and State Machines
Chapter 7 Data Processing Functions
Chapter 8 Combinational Logic and Optimization
Chapter 9 Putting the Pieces Together
Chapter 10 Evaluating A Synthesis System
Chapter 11 Future Prospects for ASIC Synthesis
Appendix A Reference Materials
-IndexA designer's guide to vhdl synthesis [texte imprimé] / Douglas E. Ott, Auteur ; Thomas J. Wilderotter, Auteur . - Boston, Dordrecht, London : Kluwer Academic Publishers, 1994 . - 306 p. : couv. ill.,ill. ; 24 cm.
ISBN : 978-0-7923-9472-3
Langues : Anglais (eng)
Catégories : MICRO INFORMATIQUE Index. décimale : 24-03 Programmation des microsystèmes et microprocesseurs Résumé : A Designer's Guide to VHDL Synthesis is intended for both design engineers who want to use VHDL-based logic synthesis ASICs and for managers who need to gain a practical understanding of the issues involved in using this technology. The emphasis is placed more on practical applications of VHDL and synthesis based on actual experiences, rather than on a more theoretical approach to the language.
VHDL and logic synthesis tools provide very powerful capabilities for ASIC design, but are also very complex and represent a radical departure from traditional design methods. This situation has made it difficult to get started in using this technology for both designers and management, since a major learning effort and `culture' change is required. A Designer's Guide to VHDL Synthesis has been written to help design engineers and other professionals successfully make the transition to a design methodology based on VHDL and log synthesis instead of the more traditional schematic based approach. While there are a number of texts on the VHDL language and its use in simulation, little has been written from a designer's viewpoint on how to use VHDL and logic synthesis to design real ASIC systems. The material in this book is based on experience gained in successfully using these techniques for ASIC design and relies heavily on realistic examples to demonstrate the principles involved.Note de contenu : Contents
Chapter 1 Introduction
Chapter 2 Making the Transition to VHDL Synthesis
Chapter 3 VHDL Background for Synthesis
Chapter 4 Synthesis of Sequential Circuits
Chapter 5 Sequential Counter Applications
Chapter 6 Control Logic and State Machines
Chapter 7 Data Processing Functions
Chapter 8 Combinational Logic and Optimization
Chapter 9 Putting the Pieces Together
Chapter 10 Evaluating A Synthesis System
Chapter 11 Future Prospects for ASIC Synthesis
Appendix A Reference Materials
-IndexExemplaires(1)
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Titre : Digital Systems Design and Prototyping : using field programmable logic and hardware description languages Type de document : texte imprimé Auteurs : Zoran Salcic, Auteur ; Asim Smailagic, Auteur Mention d'édition : 2nd. ed. Editeur : Boston, Dordrecht, London : Kluwer Academic Publishers Année de publication : 2000 Importance : 620 p. Présentation : couv. ill.,ill. Format : 24,1 cm. Accompagnement : CD-ROM ISBN/ISSN/EAN : 978-0-7923-7920-1 Langues : Anglais (eng) Catégories : MICRO INFORMATIQUE Mots-clés : Hardware Hardware beschreibungssprache Rapid Prototyping Standard VHDL Verilog design logic microprocessor Index. décimale : 24-04 Applications des microsystèmes et des micro-ordinateurs Résumé : Digital Systems Design and Prototyping: Using Field Programmable Logic and Hardware Description Languages, Second Edition covers the subject of digital systems design using two important technologies: Field Programmable Logic Devices (FPLDs) and Hardware Description Languages (HDLs). These two technologies are combined to aid in the design, prototyping, and implementation of a whole range of digital systems from very simple ones replacing traditional glue logic to very complex ones customized as the applications require.
Three HDLs are presented: VHDL and Verilog, the widely used standard languages, and the proprietary Altera HDL (AHDL). The chapters on these languages serve as tutorials and comparisons are made that show the strengths and weaknesses of each language.
A large number of examples are used in the description of each language providing insight for the design and implementation of FPLDs.
With the addition of the Altera UP-1 prototyping board, all examples can be tested and verified in a real FPLD.
Digital Systems Design and Prototyping: Using Field Programmable Logic and Hardware Description Languages, Second Edition is designed as an advanced level textbook as well as a reference for the professional engineer.Note de contenu : Contents
Preface to the Second Edition.
1. Introduction to Field Programmable Logic Devices.
2. Examples of Major FPLD Families.
3. Design Tools and Logic Design with FPLDS.
4. Introduction to Design Using AHDL.
5. Advanced AHDL.
6. Design Examples.
7. SIMP - A Simple Customizable Microprocessor.
8. Rapid Prototyping Using FPLDS - Vuman Case Study.
9. Introduction to VHDL.
10. Objects, Data Types and Processes.
11. VHDL and Logic Synthesis.
12. Example Designs and Problems.
13. Introduction to Verilog HDL.
14. Verilog and Logic Synthesis by Examples.
15. A Verilog Example: Pipelined SimP.
Index.Digital Systems Design and Prototyping : using field programmable logic and hardware description languages [texte imprimé] / Zoran Salcic, Auteur ; Asim Smailagic, Auteur . - 2nd. ed. . - Boston, Dordrecht, London : Kluwer Academic Publishers, 2000 . - 620 p. : couv. ill.,ill. ; 24,1 cm. + CD-ROM.
ISBN : 978-0-7923-7920-1
Langues : Anglais (eng)
Catégories : MICRO INFORMATIQUE Mots-clés : Hardware Hardware beschreibungssprache Rapid Prototyping Standard VHDL Verilog design logic microprocessor Index. décimale : 24-04 Applications des microsystèmes et des micro-ordinateurs Résumé : Digital Systems Design and Prototyping: Using Field Programmable Logic and Hardware Description Languages, Second Edition covers the subject of digital systems design using two important technologies: Field Programmable Logic Devices (FPLDs) and Hardware Description Languages (HDLs). These two technologies are combined to aid in the design, prototyping, and implementation of a whole range of digital systems from very simple ones replacing traditional glue logic to very complex ones customized as the applications require.
Three HDLs are presented: VHDL and Verilog, the widely used standard languages, and the proprietary Altera HDL (AHDL). The chapters on these languages serve as tutorials and comparisons are made that show the strengths and weaknesses of each language.
A large number of examples are used in the description of each language providing insight for the design and implementation of FPLDs.
With the addition of the Altera UP-1 prototyping board, all examples can be tested and verified in a real FPLD.
Digital Systems Design and Prototyping: Using Field Programmable Logic and Hardware Description Languages, Second Edition is designed as an advanced level textbook as well as a reference for the professional engineer.Note de contenu : Contents
Preface to the Second Edition.
1. Introduction to Field Programmable Logic Devices.
2. Examples of Major FPLD Families.
3. Design Tools and Logic Design with FPLDS.
4. Introduction to Design Using AHDL.
5. Advanced AHDL.
6. Design Examples.
7. SIMP - A Simple Customizable Microprocessor.
8. Rapid Prototyping Using FPLDS - Vuman Case Study.
9. Introduction to VHDL.
10. Objects, Data Types and Processes.
11. VHDL and Logic Synthesis.
12. Example Designs and Problems.
13. Introduction to Verilog HDL.
14. Verilog and Logic Synthesis by Examples.
15. A Verilog Example: Pipelined SimP.
Index.Exemplaires(1)
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