| Titre : |
Logic synthesis using synopsys |
| Type de document : |
texte imprimé |
| Auteurs : |
Pran KURUP, Auteur ; Taher ABBASI, Auteur |
| Editeur : |
Kluwer Academic Publishers |
| Année de publication : |
1997 |
| Importance : |
322 p. |
| Présentation : |
ill. |
| Format : |
24 cm. |
| ISBN/ISSN/EAN : |
978-1-4612-8634-9 |
| Note générale : |
Referen. Index. |
| Langues : |
Anglais (eng) |
| Catégories : |
ELECTRONIQUE:Electronique numérique
|
| Mots-clés : |
VHDL ,RTL,TEXTIO,FPGA,CAD,synthesis using synopsys |
| Index. décimale : |
09-10 Electronique numérique |
| Résumé : |
ogic Synthesis Using Synopsys, Second Edition, is for anyone who hates reading manuals but would still like to learn logic synthesis as practiced in the real world. This book should help the reader develop a better understanding of the logic synthesis design flow, optimization strategies using the Design Compiler, test synthesis using the Test Compiler, commonly used interface formats such as EDIF, SDF and PDEF, Links from the Design Compiler to Layout Tools, the FPGA synthesis process, design re-use in a synthesis-based design methodology and a conceptual introduction to behavioral synthesis. Examples in both VHDL and Verilog have been provided throughout the book. Logic Synthesis Using Synopsys, Second Edition covers several new and emerging areas in addition to improvements in the presentation and contents in chapters from the first edition.
sommaire :
High-level design methodology overview 1
VHDL/verilog coding for synthesis 33
Pre and post-synthesis simulation 75
Constraining and optimizing designs -197
Constraining and optimizing designs II 139
Links to layout 175
FPGA synthesis 197
Design for testability 209
Interfacing between CAD tool 245
Design re-use using design ware263
Behavioral synthesis-an introduction 283
|
Logic synthesis using synopsys [texte imprimé] / Pran KURUP, Auteur ; Taher ABBASI, Auteur . - Kluwer Academic Publishers, 1997 . - 322 p. : ill. ; 24 cm. ISBN : 978-1-4612-8634-9 Referen. Index. Langues : Anglais ( eng)
| Catégories : |
ELECTRONIQUE:Electronique numérique
|
| Mots-clés : |
VHDL ,RTL,TEXTIO,FPGA,CAD,synthesis using synopsys |
| Index. décimale : |
09-10 Electronique numérique |
| Résumé : |
ogic Synthesis Using Synopsys, Second Edition, is for anyone who hates reading manuals but would still like to learn logic synthesis as practiced in the real world. This book should help the reader develop a better understanding of the logic synthesis design flow, optimization strategies using the Design Compiler, test synthesis using the Test Compiler, commonly used interface formats such as EDIF, SDF and PDEF, Links from the Design Compiler to Layout Tools, the FPGA synthesis process, design re-use in a synthesis-based design methodology and a conceptual introduction to behavioral synthesis. Examples in both VHDL and Verilog have been provided throughout the book. Logic Synthesis Using Synopsys, Second Edition covers several new and emerging areas in addition to improvements in the presentation and contents in chapters from the first edition.
sommaire :
High-level design methodology overview 1
VHDL/verilog coding for synthesis 33
Pre and post-synthesis simulation 75
Constraining and optimizing designs -197
Constraining and optimizing designs II 139
Links to layout 175
FPGA synthesis 197
Design for testability 209
Interfacing between CAD tool 245
Design re-use using design ware263
Behavioral synthesis-an introduction 283
|
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